Monthly Archives: November 2015

How modern multi-processor multi-Root Complex system assigns PCI bus number

Nowadays multi-processor systems is becoming more and more common especially in high performance computing. Things become interesting when you think about it from PCI Bus perspective: We use to model it as one PCI host bridge (root complex) yet now … Continue reading

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PCI Express Max Read Request, Max Payload Size and why you care

Modern high performance server is nearly all based on PCIE architecture and technologies derived from it such as Direct Media Interface (DMI) or Quick Path Interconnect (QPI). For example below is a sample block diagram for a dual processor system: … Continue reading

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